Circuit designers of multi-Gigabit systems face a number of challenges as advances in technology mandate increased performance in high-speed components. For example, chip-to-chip data rates have traditionally been constrained by the bandwidth of input/output (I/O) circuitry in each component. However, process enhancements (e.g., transistor bandwidth) and innovations in I/O circuitry have forced designers to also consider the effects of the transmission channels between the chips on which data is sent.
At a basic level, data transmission between components within a single semiconductor device or between two devices on a printed circuit board may be represented by the system 10 shown in FIG. 1A. In FIG. 1A, a transmitter 12 (e.g., a microprocessor) sends data over channel 16 (e.g., a copper trace on a printed circuit board or “on-chip” in a semiconductor device) to a receiver 14 (e.g., another processor or memory). When data is sent from an ideal transmitter 12 to a receiver 14 across an ideal (lossless) channel 16, all of the energy in a transmitted pulse will be contained within a single unit interval (UI).
However, real transmitters and real transmission channels do not exhibit ideal characteristics, and as mentioned above, the effects of transmission channels are becoming increasingly important in high-speed circuit design. Due to a number of factors, including, for example, the limited conductivity of copper traces, the dielectric medium of the printed circuit board (PCB), and the discontinuities introduced by vias, the initially well-defined digital pulse will tend to spread or disperse as it passes through the channel 16. This is shown in FIG. 1B. As shown, a single pulse of data 15a is sent by the transmitter 12 during a given UI (e.g., UI3). However, because of the effect of the channel 16, this data pulse 15b becomes spread over multiple UIs at the receiver 14, i.e., some portion of the energy of the pulse is observed outside of the UI in which the pulse was sent (e.g., in UI2 and UI4). This residual energy outside of the UI of interest may perturb a pulse otherwise occupying the neighboring UIs, in a phenomenon referred to as intersymbol interference (ISI).
Because of the potentially negative impact of ISI on the reliability of data transfer and detection at the receiver 14, such data transfer is often simulated in a computer system using simulation software. The design of a high-speed system 10 typically involves iterations of circuit-level simulation to ascertain whether or not the system 10 has performed error free communication, and this of course requires a waveform suitable for simulation in simulation software. Simulation is a valuable tool in the semiconductor industry, where it is generally very expensive to design and produce a given integrated circuit. The use of simulation software allows the circuit designer to verify the operation and margins of a circuit design before incurring the expense of actually building and testing the circuit. Through the use of simulations, design errors or risks are hopefully identified early in the design process, and resolved prior to fabrication. Unfortunately, modeling and simulation of realistic waveforms suitable to accurately reflect the characteristics of a signal is difficult. It is generally necessary to define a waveform in a layout simulator such as SPICE™. This requires transistors, resistors, and other discrete components to be electronically considered, even if they are not actually yet constructed or laid out. Such component-level consideration takes considerable time and effort.
One standard application for simulating systems and signals is Verilog. Verilog is a hardware description language (HDL) used to describe electronic systems and the signals that propagate in such systems, at various levels of abstraction. A common use for Verilog in relationship to circuit-level simulation involves the use of piecewise-linear (PWL) signals to represent various signals. PWL signals in Verilog hold a value for a given time before changing to a new value. One or more PWL signals in Verilog are represented by a single vector file, which contains necessary timing information for each signal contained in the vector file. Verilog, like other HDLs, is designed to stress digital circuits. Accordingly, Verilog PWL signals typically represent several parallel signals, which may include instructions, memory addresses, random data, etc. Typically the instructions and memory address signals are limited by the permissible instruction set or valid address space.
There are at least two reasons for simulating so many signals simultaneously. First, the state machine that controls the operation of the integrated circuit may require several inputs to function. Second, in many instances it is important to verify the relative timing of such signals, particularly when the possibility of race conditions exists. The term race condition refers to a situation where multiple digital signals must arrive at a point in the circuit with a specific timing relationship (e.g. a particular order of arrival). Race conditions become problematic when signal propagation along different paths results in the violation of the required timing, and hence circuit malfunction. Because HDL input is often idealized, the only factors usually considered when looking for race conditions are the propagation delays through the various circuits and interconnects. Thus, the effects of random timing variations (e.g., jitter), are usually not considered. While it is possible to manually offset the timing of the various input signals to approximate jitter, no method has been introduced for translating HDL input into a data set exhibiting realistic, statistically defined jitter.
FIG. 2A shows a table 18 containing time and voltage values (i.e., signal information) for forming two separate, parallel PWL data signals IN1 21a and IN2 22a. As seen in FIG. 2A, only the times of transitions and the corresponding logic values following the transitions (i.e., ‘0’ and ‘1’), are included in the table. One skilled in the art will appreciate, of course, that other information, such as a rise time or a fall time for signal transitions may also be present, and that all signal information (i.e., for both data signals) is typically encoded in a single vector file that is interpretable by Verilog. In other words, a “master” rise or fall time may be designated for a signal, such that the rise or fall time is incorporated into each signal transition.
To summarize, at 0 nanoseconds, each of the data signals IN1 21a and IN2 22a begins at a logic value of ‘0.’ At 1.0 nanoseconds, the first data signal IN1 21a transitions from a logic value of ‘0’ to ‘1,’ while the other data signal IN2 22a remains at a logic value of ‘0,’ which is inferred by the fact that the reported voltage does not change. At 1.5 nanoseconds, data signal IN2 22a transitions from a logic value of ‘0’ to ‘1,’ while IN1 21a remains at a logic value of ‘1’ Finally, at 1.7 nanoseconds, data signal IN1 21a transitions from a logic value of ‘1’ back to ‘0,’ while IN2 22a remains at a logic value of ‘1.’ Such data signals IN1 21a and IN2 22a may be used, for example, as command signals in a simulated microprocessor. A graph corresponding to each of the aforementioned data signals is shown in FIG. 2B. As can be seen in FIG. 2B, the PWL data signals represented by the table in FIG. 2A can form two distinct data signals, and, as expected, a transition for each of these data signals occurs at the ideal time indicated by the times shown in the table of FIG. 2A. The logic values shown in FIG. 2A may be inferred as logic or voltage values by the program that interprets the sparse PWL voltage versus timing information shown in FIG. 2A, depending on the availability of such voltage reference information with the sparse PWL voltage versus timing information. In other words, as should be understood, the logic values of ‘0’ and ‘1’ refer to high and low reference voltages for the signals.
One concern among system designers is that modeling and simulation using such signals may not provide a suitably accurate picture of how the system 10 will process real signals. Realistic data signals are not ideal, but instead suffer from various sources of amplitude noise and timing jitter, which may vary randomly between the bits of data. Regardless of the source or type of amplitude noise or timing jitter, it is difficult to quickly and efficiently simulate the effects of amplitude noise and timing jitter in the context of a system 10, which is especially problematic.
The challenge associated with simulating channel-affected signals is highly correlated to the characteristics of the degradation affecting the channel. Signals in any transmission medium experience both random and deterministic degradation. Random degradation, in the form of random Gaussian distributed amplitude noise and timing jitter, which stem from thermal and shot noise, requires statistical quantification. Similarly, deterministic amplitude noise and timing jitter are linked to several sources including power supply noise, inter-channel crosstalk, impedance discontinuities, component variance, and at high frequencies the response of the channel. These factors result in a variety of observable characteristics, from periodicity to uncorrelated-bounded randomness. To model these noise components correctly requires the ability to designate their probability during the noise generation stage and consequently inject or superimpose these effects onto the underlying signal in a way reflecting what occurs in the actual system. The final success or robustness of a particular design is dependent, to a large measure, on the achieved realism of the simulation environment.
To date, industry standard simulators do not provide the level of amplitude noise and timing jitter generation control necessary to model a realistic communication channel, though some jitter adding features have recently become available. Agilent's Advanced Design System (ADS) tool, Synopsys's Hspice, and Synapticad's WaveformerPRO all offer stock waveforms with additive jitter, but the features are limited in several ways. For example, in the cases of ADS and Hspice, the jitter exhibited by the waveform may take on one of a few standard forms: it may either exhibit a Gaussian probability distribution or a periodic jitter distribution (e.g. sinusoidal distribution, etc.), but combinations of random and periodic jitter distributions are limited both in terms of the number of permitted jitter sources per signal and the peak magnitude of the jitter. In addition, there is no clear mechanism for adding amplitude noise in the time-domain. WaveformerPRO permits even fewer options, allowing the user to define a peak-to-peak jitter value, but offering no control over the statistical characteristics of the jitter. While all three tools provide jittery clock sources, only Agilent's tool allows for jitter to be added to random data sequences. While random data may be manually altered by the user, the length of a user defined sequence is limited to (232−1) bits. Thus, while one can find clock and random data sources exhibiting a limited selection of jitter characteristics, a tool has yet to be developed to produce simulatable waveforms of arbitrary data patterns and of arbitrary length, exhibiting arbitrary timing jitter and amplitude noise characteristics.
Another challenge in simulating realistic signaling environments is tied to the underlying statistical assumption that sufficient samples of the behavior to be characterized are readily available. As such, it is becoming necessary to include more and more cycles with each simulation. As the relative size of each individual noise component is very small with respect to the overall cycle period, fine voltage and timing resolution are necessary. While the timing resolution of a simulation may be enhanced by decreasing the time span between each calculation (i.e., the simulated time step), this leads to a simultaneous increase in both the simulation run time and the memory requirement. When fine simulation resolution is coupled with a greater number of simulated cycles, the result is an enormous amount of data and prohibitively lengthy simulation times. It is not uncommon for transistor-level transient (time-based) simulations to run for hours or even days. It is likewise not uncommon for such a simulation to fail due to a lack of memory resources.
In addition to the requirement of picosecond timing resolution, the statistical nature of random amplitude noise and timing jitter demand that the signal-system interaction be computed over several clock cycles in order to provide the necessarily large number of samples required to properly build up probability distributions. Coupling the constraints of high resolution (small transient time step) with the need to observe the behavior over thousands or millions of cycles extends the transistor-level simulation run time and memory requirements even further.
While unbounded Gaussian noise and jitter lead to long term bit errors, depending upon the bandwidth of the channel, ISI and the corresponding data-dependent jitter (DDJ) may dominate the short term signal degradation. Methods have been proposed for predicting the DDJ distribution from the relationship of the data-rate and the channel bandwidth.
With the following background in hand, it should be apparent that an improved signal simulation technique would at least allow for the simulation of various kinds of and lengths of signals, with good computational efficiency, and allow for the formation of a signal for simulation in which amplitude noise and timing jitter of any resolution are easily and realistically modeled. The disclosed techniques achieve such results in a manner easily implemented in a typical computerized system or other computerized circuit simulation software package.